Recently Xilinx caught my attention with the announcement of their next generation Virtex and Spartan FPGA platforms. Having worked with the Spartan series I was really excited to see the version number double (!) from 3 to 6. Yes, say hello to Spartan-6. And...Virtex-6 of course but I'm focusing on the low-cost family for now since it got the overall (and long awaited) face lift.
The first three things I've noticed were (1) the addition of serial transceivers, (2) an increased MUL : LUT ratio and (3) memory controller/PCIe endpoint blocks. Finally! Finally, Xilinx made it and added built-in support for high-speed serial communication. No need to look over with envy at Altera or Lattice with their low-cost families anymore...wait a minute. Altera announced new Arria II GX devices and Lattice is about to release the ECP3M family. But don't expect a comparison now. More or less, the three points apply to all low-cost families across vendors:
(1) The Spartan-6 platform is split into two classes: seven devices without high-speed serial I/O and four devices with 2 / 4 / 8 GTP low-power transceivers/PCIe. While Altera and Lattice are pushing the second generation of low-cost devices with serial transceivers out of the door it's Xilinx first device in the price-sensitive market. And it's time. High-speed serial connectivity is becoming the emerging standard in complex embedded systems. And believe me systems will get even more complex and demand more bandwidth in the future. To overcome complexity and reduce development time vendors need to support a well established communication standard. And what USB is for the desktop market will PCIe become for embedded/industrial applications.
(2) Marketing folks identified mass market audio and video applications as typical innovation areas. These applications are driven by digital signal processing (DSP) and require lots of computing power. So give 'em multipliers + accumulators aka DSP slices aka (sys)DSP blocks! That's my second point: an increased number of multipliers per logic resources. Up to 182 DSP48E1 slices in the biggest Spartan-6 devices are waiting for your DSP algorithms. And DSP is everywhere especially inside todays FPGAs. Or are you (mis)using them for glue-logic?
(3) Memory controller blocks are just another step towards systems-on-chip. They'll become handy when synthesizing a soft CPU core into the fabric or when large amounts of data need to be buffered. Lattice had them already built in the ECP2M Programmable I/O. They really set the benchmark in the price-sensitive market then. I can imagine that Xilinx lost some customers to Lattice here...
However, competition goes on. You can meet all three FPGA vendors at embedded world in Nuremberg this week from Tuesday to Thursday (3.-5 March 2009) and give them feedback on their latest technology.